1. Field of the Invention
The present invention relates to an integrated circuit, a device and a method for inputting/outputting images, in particular, the present invention relates to the improvement of an art to avoid data conflict at the time of data transfer among a plurality of memories in a case where the integrated circuit possesses a plurality of DMA (Direct Memory Access) controllers.
2. Description of the Related Art
In recent years, a system LSI (Large Scale Integrated Circuit) that possesses in itself a processor for controlling programs and an integrated circuit for image input/output units has been developed, due to advanced semiconductor processing using thinner lines.
FIG. 10 is a block diagram illustrating a system LSI 1 for image processing and an image input/output device utilizing the system LSI 1, according to an prior art.
In FIG. 10, the system LSI 1 comprises with a bus 2, a processor 3 (that may be substituted by a plurality of processors in some cases) connected with the bus 2, a DMA controller 6, an image input unit 8 and an image output unit 9. The image input unit 8 possesses a synchronizing signal detector 10 and an input buffer memory 11, while the image output unit 9 possesses a synchronizing signal generator 12 and an output buffer memory 13.
A main memory 4 and a non-volatile memory 5 are connected with the bus 2 of the system LSI 1. An image input device 14 such as a CCD camera is connected with the image input unit 8, while an image display device 15 such as a liquid crystal display is connected with the image output unit 9.
The processor 3 controls the image input/output device by reading and executing programs stored in the non-volatile memory 5. One example of the control will be described below.
In FIG. 10, an image input signal from the image input device 14 is inputted into the synchronizing signal detector 10 in the image input unit 8. In the synchronizing signal detector 10, a synchronizing signal is detected, and at the same time, effective image data that is an image signal effective in displaying is extracted and temporarily stored in the input buffer memory 11.
The effective image data temporarily stored in the input buffer memory 11 is transferred via the bus 2 and stored into the main memory 4. Then necessary processing such as compressing the image, expanding the image, etc. will be performed by the processor 3. Such processed effective image data is again stored in the main memory 4 via the bus 2.
The effective image data stored in the main memory 4 is sent to and stored temporarily in the output buffer memory 13 of the image output unit 9. The effective image data read from the output buffer memory 13 is combined with a synchronizing signal in the synchronizing signal generator 12. The synchronizing signal combined effective image data is then sent to the image display device 15 to be displayed.
At this time, the DMA controller 6 controls to transfer data via the bus 2; the data to be read from and/or to be stored in the main memory 4, the non-volatile memory 5, the input buffer memory 11, and the output buffer memory 13.
One example of such operations will be described in more detail with reference to FIG. 10 and FIG. 11.
FIG. 11 is a chart exemplifying DMA timing of a system LSI for image processing according to the prior art. As shown in FIG. 11, effective image data 21 is extracted and generated continuously in the image input unit 8 at a non-blanking period of a vertical synchronizing signal 20, from the image input signal inputted from the image input device 14 shown in FIG. 10. Thereafter the effective image data 21 is temporarily stored in the input buffer memory 11. The effective image data 21 temporarily stored in the input buffer memory 11 is to be transferred to the main memory 4 continuously at the predetermined time, for example, synchronizing with a horizontal synchronizing signal. At this time, upon receipt of a request from the image input unit 8 to transfer the effective image data 21 to the main memory 4, the DMA controller 6 operates so that the effective image data is transferred at top priority while interrupting processing of lower priority.
When displaying on the image display device 15 the image data that has been processed and stored in the main memory 4, the DMA controller 6 transfers the effective image data 23 to the output buffer memory 13 from the main memory 4 at top priority at the predetermined time continuously, for example, synchronizing with a horizontal synchronizing signal at a non-blanking period of a vertical synchronizing signal 22 as shown in FIG. 11.
Thus, the image data transfer from the input buffer memory 11 to the main memory 4 and the image data transfer from the main memory 4 to the output buffer memory 13 are both processed at top priority with interrupting the processing of lower priority. At this time, the DMA controller 6 arbitrates according to the timing scheduled beforehand so that such image data transfer may not conflict with other data transfer in the bus 2.
The processing of data transfer at the predetermined time at top priority as described above is called “urgent processing”, while other processing of data transfer, for example, between the processor 3 and the main memory 4 when processing image such as image compressing and image expanding, is called “normal processing”.
A main memory path occupancy state chart 24 shown in FIG. 11 indicates an example of scheduling by the DMA controller 6. In this example, image data is transferred alternately as “urgent processing” at the predetermined time in the continuous order that a (J) line of an (M) frame to the image output unit 9, an (I) line of an (N) frame from the image input unit 8, a (J+1) line of the (M) frame to the image output unit 9, and an (I+1) line of the (N) frame from the image input unit 8, while other process by the processor 3 is performed as “normal processing”.
A part 25 of the main memory path occupancy state chart 24 in FIG. 11 is enlarged in FIG. 12. That is, FIG. 12 shows an enlarged chart of DMA timing of the system LSI 1 for image processing according to the prior art. This figure shows timing in scheduling the main memory path occupancy state. In the example shown in FIG. 12, a first DMA processing 26 of the processor 3 as “normal processing” is interrupted, and a DMA processing 27 of a (J+1) line and a DMA processing 28 of an (I) line as “urgent processing” are performed. Thereafter a first DMA processing 29 of the processor 3 as “normal processing” is resumed, and then a second DMA processing 30 of the processor 3 as “normal processing” is performed successively.
The first DMA processing 26 of the processor 3 is first data transfer processing between the processor 3 and the main memory 4. The DMA processing 28 of the (I) line is the data transfer processing of the (I) line of the (N) frame from the input buffer memory 11 to the main memory 4. The DMA processing 27 of the (J+1) line is the data transfer processing of the (J+1) line of the (M) frame from the main memory 4 to the output buffer memory 13. Other parts of the main memory path occupancy state chart 24 will be understood in a similar way.
Controlling the interruption and the resumption of the normal processing mentioned above is performed by a DMA interruption/resumption control unit 7 of the DMA controller 6 shown in FIG. 10.
There are some problems in the image processing system according to the prior art described above.
First, since both image data urgently processed and image data normally processed share the single main memory 4, conflict of data transfer on the bus 2 occurs frequently. In order to avoid this situation, precise scheduling of the DMA is necessary, which makes design of the DMA scheduling complicated.
Secondly, a controlling mechanism to interrupt and resume the normal processing is necessary, which makes a circuit of the DMA controller 6 complicated.
Thirdly, the normal processing is often interrupted and hence delayed.
Fourthly, the conventional system LSI 1 having a fixed image input unit 10 and a fixed image output unit 9 can not be flexibly connected to an image input device 14 and an image display device 15 with different specifications, which lacks expandability. To meet such situations, it is necessary to develop a new system LSI having a synchronizing signal detector and a synchronizing signal generator with different specifications, which costs time and money.